1. Technical Field
Various embodiments of the inventive concept relate to a method for fabricating a semiconductor apparatus having a vertical channel.
2. Related Art
Transistors, which are typical elements in semiconductor devices, include a gate, a source, and a drain. Transistors having two-dimensional (2D) structures may include a gate formed on a semiconductor substrate, and a source and a drain formed by doping the semiconductor substrate at both sides of the gate with impurities. The region between the source and the drain becomes the channel region of the transistor. The channel length of the transistor has a limit on how much its size can be reduced based on the linewidth of the gate. When the channel length is reduced below the limit, phenomena such as a short channel effect may occur that limit the ability of the transistor to properly function.
To overcome these limitations, vertical channel semiconductor devices have been used. In the vertical channel semiconductor devices, an active pattern is formed in a pillar form, and a source and a drain are located in lower and upper portions of the pillar to form the vertical channel, which is perpendicular to the surface of the semiconductor substrate.
In vertical channel semiconductor devices, a gate is extended in a line surrounding the pillar or in contact with either side of the pillar.
However, as the above-described vertical channel semiconductor devices are scaled down, there is increased fabrication difficulty. In particular, it is difficult to control the contact resistance between a vertical channel transistor and a lower electrode in a semiconductor device having a linewidth below 20 nm. Thus, there is a need for a method for fabricating semiconductor devices having stable contact resistance.